The replacement fin process is an integration method to achieve semiconductor fins of silicon germanium (SiGe), Si1-xGex, silicon carbide (SiC), silicon germanium carbide (SiGeC), germanium (Ge), or combined group III and group IV elements (III-V). However, a defect free replacement fin approach has not been achieved on standard orientation (100) wafers with fin sidewalls and electrical transport in the <110> crystalline direction. For example, a known approach of replacement fin integration is illustrated in FIGS. 1A through 1D. Adverting to FIG. 1A, silicon (Si) fins 101 and 103 are formed on a Si substrate 105 by etching. In particular, the sidewalls of the Si fins 101 and 103 have a degree of roughness as a result of the etching process. Although exaggerated for illustration purposes, the roughness need only be on the angstrom (Å) level to provide nucleation sites for defect propagation. A shallow trench isolation (STI) layer 107 is then filled around the Si fins 101 and 103 and annealed (not shown for illustrative convenience), as depicted in FIG. 1B. Adverting to FIG. 1C, the Si fins 101 and 103 are recessed, forming recesses 109 and 111. Next, replacement SiGe fins 113 and 115 are formed in the recesses 109 and 111, respectively, by epitaxial (epi) growth, as depicted in FIG. 1D. However, the roughness at the SiGe or Ge to silicon oxide (SiO2) sidewall interface (which is transferred into the SiO2 sidewall from the Si fin prior to replacement) provides nucleation sites for defect propagation during the epi process forming the replacement SiGe fins 113 and 115.
A need therefore exists for methodology enabling formation of defect free replacement fins.